Interesting question. The currents involved are very small, so it might not be enough to destroy the chip.
One unexpected thing I noticed in the chip is a control signal to pull lines low during startup. CMOS doesn't like floating signals (since you can end up with the pull-up and pull-down transistors both on). But before the configuration is loaded, the routing lines may not be connected to anything. So the FPGA has to pull these lines low until everything is configured, and then release them.
One unexpected thing I noticed in the chip is a control signal to pull lines low during startup. CMOS doesn't like floating signals (since you can end up with the pull-up and pull-down transistors both on). But before the configuration is loaded, the routing lines may not be connected to anything. So the FPGA has to pull these lines low until everything is configured, and then release them.