You can make use of a lot more than 32 registers, but not with existing RISC or x86 instructions. If I remember correctly EPIC had global registers like your normal RISC, local registers like SPARC and support for batch renaming registers to implement software pipelines. Software pipelining can make use of a lot of registers and exploit the high IPC EPIC was supposed to provide. Still an ISA that avoids the pipeline prologue and epilogue could make software pipelining useful for a lot more algorithms ... in theory.